This invention relates to gallium arsenide (GaAs) field-effect transistors (FET's) and to methods of making such transistors. More particularly, this invention is concerned with a method for making self-aligned gate (SAG) GaAs transistors for use in the integrated circuit field.
The processes currently being used fall into two categories: (1) Thermally-Stable Refractory Gate (RG), and (2) Substitutional Gate (SG). From a processing standpoint, the RG process is simpler and easier to manufacture than the SG process, but it places stringent requirements on the thermal stability of the Schottky gate metallization. The SG approach places no unusual thermal stability requirements on the gate metal but does require the difficult formation of a tri-layer gate substitution mask with a carefully controlled T-shaped profile.
While the RG approach may be superior overall to the SG approach, previous embodiments of the RG approach have suffered the need to compromise some aspects of the process due to inadequate technology. One major problem in the past has been that the thermal stability of the gate metal is insufficient to permit annealing of the self-aligned n+ implant at temperatures higher than 750.degree. C.-800.degree. C., whereas optimum activation of the channel implants of the device occurs at temperatures above 800.degree. C. and are generally in the range between about 810.degree. C.-850.degree. C. for furnace anneals and generally above 900.degree. C. for RTA (rapid thermal annealing). This necessitates one of two possible compromises: either annealing both the initial channel implant and the subsequent device region at an annealing temperature compatible with the n+ implanted regions, or doing two separate anneals, a channel anneal before gate formation at an optimum time-temperature product and then a source/drain anneal at a lower than optimum temperature. In either case, the implant activation and electron mobility in the source and drain implant regions suffer, so that the FET characteristics are less than optimum.
Another disadvantage of some embodiments of the RG approach is the use of a photoresist mask to plasma etch the refractory gate metal. Thus, since this approach results in an FET without an overhanging "T-gate" structure, it allows no means to space the position of the gate from the edges of the self-aligned n+ regions, and therefore no means to optimize the gate structure simultaneously with respect to both capacitance (Cgd) and series resistance.
In the SG process, gold is used as the refractory metal since it exhibits low resistivity and its thermal stability is sufficient for that process. However, in the RG process, the refractory metals used must be such that they can achieve the necessary thermal stability of the gate Schottky contact. Gold is not a suitable metal for this process. Another problem in the past has been the high resistivity of the refractory metals suitable for the RG process relative to that of gold. The high resistivity of the refractory gate metallization complicates the RG approach in that the first level interconnect metal, which must have lower resistivity than possible with a refractory metal, is defined by an additional mask level rather than the gate mask level as in the SG process. Also the high gate resistance degrades the performance of RG processed FET's, which precludes using this highly manufacturable process to fabricate high frequency analog circuits.
Previous SAG FET's have employed a symmetrical structure, with highly doped n+ regions on either side of the self-aligned gate electrode. Although this structure is relatively simple to fabricate, it has several disadvantages. First, the close proximity of the implanted n+ drain region to the drain side of the gate causes a large reduction in the gate-drain breakdown voltage, which severely limits the ultimate power-handling capability of the FET. Furthermore, the high doping of the implanted n+ drain region and its proximity to the gate metallization increases the gate-drain capacitance. Finally, the close spacing between source and drain n+ regions increases the parasitic substrate current, thereby decreasing the output resistance of the FET. All of these have adverse effects on the performance of a self-aligned FET when used in either analog or digital circuits, but the use of a self-aligned FET to handle high-frequency analog signals is particularly impaired by the above disadvantages of a symmetrical device structure.
It is therefore an object of the present invention to provide a self-aligned gate type GaAs field-effect transistor which overcomes the disadvantages of the prior art.
It is an additional object of the present invention to provide a refractory gate metallization with high thermal stability.
It is yet another object of the present invention to provide a method of manufacturing a GaAs field-effect transistor using a single annealing step.
It is an additional object of the present invention to provide a method of producing GaAs field-effect transistors in which the manufacturing yield is increased and the product cost is decreased.
It is still a further object of the invention to provide a GaAs FET manufacturing process which permits the use of a high-resolution positive photoresist to define a metal etch mask in a liftoff sequence.
It is another object of the present invention to provide a FET which allows gate line widths of 1 micrometer or less to be easily defined optically.
It is yet another object of the present invention to provide an oversize metal mask for gate definition which serves as an implant mask for highly doped source and drain implants thereby allowing the creation of an implant-to-implant spacing larger than the gate length.
It is an additional object of the invention to provide a refractory gate metallization which simultaneously provides both a high-temperature stable Schottky barrier and an equally high-temperature stable diffusion barrier between gold (Au) and GaAs.
It is still another object of the invention to provide a diffusion barrier to Au at operating temperature to improve device lifetime from an electromigration perspective especially for Power FET's, i.e. up to 2 watts or more and 800 mw/mm of gate periphery (gate width).
It is a still further object of the present invention to permit the use of Au as an etch mask to fabricate a T-gate structure for use as a self-aligned implantation mask and leave the Au in place during the activation anneal to reduce the gate resistance of the FET.
It is yet another object of the present invention to use a refractory metal/Au layered structure for simultaneous formation of both the gate metal and first-level interconnect metal to increase the throughput of GaAs IC's and reduce the cost of fabrication.
It is another object of the present invention to improve the high frequency performance of refractory gate GaAs FET's by reducing the gate resistance.
It is yet another object of the invention to allow the application of the highly manufacturable RG process to the fabrication of analog FET's and MMICS.
A further object is to provide a SAG FET gate metallization which has very low gate resistance.
Still a further object of the invention is to fabricate SAG analog and digital FET's on the same integrated circuits.
Another object of the invention is to planarize a dielectric anneal encapsulant overlying a first level gate metallization of refractory metal by plasma etching to expose the top of the first layer gate metallization prior to formation of a second layer of gate metallization.
It is an additional object of the present invention to provide a self-aligned device structure in which a highly doped n+ region is present between the source and gate electrodes, but is not present in a channel region laterally adjacent to the gate electrode on the drain side of the gate.
It is an additional object of the present invention to provide a method of producing self-aligned gate field-effect transistors in which the output resistance and the gate-drain breakdown voltage are increased and the gate-drain capacitance is decreased.
It is also an object of the invention to provide a method of producing FET's having improved source-drain breakdown voltage.
It is another object of the invention to provide an FET which allows gate line widths of 1 micron or less to be easily defined optically, using 1 micron masks.
These and other objects of the invention which will become apparent hereinafter are accomplished by the present invention which provides a process for making a field-effect transistor comprising one or more of the structural and process innovations of the present invention including: (i) the step of heating a gallium arsenide substrate having first channel forming and second source-drain forming ions implanted therein and a high temperature resistant metallization layer used to self-align the source and drain implants, where the metallization layer includes 1 to 20 atomic percent titanium and includes tungsten, and the metallization layer is deposited on the substrate and heated to a high temperature sufficient to anneal the ion implanted regions of the substrate and activate the ions implanted therein; (ii) the step of forming a gate metallization layer on said substrate which layer is fabricated from titanium-tungsten nitride (TiWN.sub.x) and is used both as a diffusion barrier between a gold conductor and the GaAs channel of the transistor and as a Schottky junction forming refractory gate; (iii) masking of a portion of the channel region on the drain side of the gate electrode before performing an n+ self-aligned source and drain implant, so that the n+ implanted source-drain region is asymmetrical on the two sides of the gate electrode to obtain minimum desired parasitic source resistance, without the deleterious effects on gate-drain breakdown voltage, gate-drain capacitance, source-drain breakdown voltage, and output resistance that accompany a high doping level adjacent to the drain side of the gate; iv) overcoming the disadvantage of the high gate resistance for a Thermally-Stable Refractory Gate SAG FET while maintaining large alignment tolerances and reducing gate resistance by including a second gate metallization layer, which has a higher conductivity than the refractory gate layer and which may be formed after the n+ self-aligned source/drain implant and preferably after the activation anneal thus precluding degradation of the conductivity of the second gate metal by interdiffusion with the first (refractory) gate metal during activation. A large tolerance for misalignment of the gate mask level may be obtained by a planarization etch of the anneal cap which is continued long enough to expose the top surface of the first gate metallization. This may be done without any initial aperture delineation for the gate since the vertical height of the gate metal causes the gate to be the highest physical structure on the chip surface and thus to become exposed first during the planar etch. The remaining encapsulant adjacent the sides of the first gate metallization layer then acts as an insulator over the FET channel region and other portions of the substrate and allows for gross misalignment (.+-.0.5 micron) of the second gate metallization layer without FET performance degradation. Using this innovation for reducing resistance in a refractory gate substantially increases performance of self-aligned GaAs devices while maintaining the basic simplicity of the RG process.